Research Assistant Resumes in US: Alekya

Research Assistant Resume

Contact Candidate

Name:

Alekya

Location:

Experience:

1-3 yrs

Most Recent Job Title:

Research Assistant

Objective:

To obtain a full time position in Electrical Engineering involving Digital Designing/ VLSI
Design/ASIC Design/Analog Design/RF/DSP.

Resume Text:

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e, software and system designer

· Good communication skills, highly motivated, goal-oriented team player with excellent problem solving and leadership skills

· Deep passion for excellence, leading people and resources efficiently.

TECHNICAL SKILLS:

Programming Languages: C, C++, 8085/8086 Assembly Languages, Parallel Programming (M.P.I), Visual Basic (6.x), Matlab, Oracle 8.x/9.x, ARM Compiler.

Operating systems: UNIX, AIX, Windows and LINUX.

Hardware Design Language: VHDL, Verilog.

Synthesis Tools: Design Compiler, Physical Compiler, Ambit, PKS,.

Timing Tool: Primetime

Testability Tools: Mentor Dft, flextest, fastscan, MbistArchitect, BistArchitect

Simulation Tools: Vcs, Ncverilog, Modelsim, Verilog-XL, Hspice, Nana Sim, Pspice, Avant Waves

Place&Route Tools: Cadence Gate Ensemble, Silicon Ensemble, First Encounter

Schematic/Layout Entry tools: Cadence Virtuoso, Magic 6.0, Analog Artist

Drc/Lvs Tools: Cadence Dracula, Opus, Synopsys Hercules, Mentor Calibredrv

FPGA Software: Xilinx Foundation Series, Altera MAX PLUS

Scripting : Perl, Awk, Sed, Shell scripting (C shell, Korn shell )

EDUCATION

Master of Science in Electrical Engineering GPA 3.82/4.0

University of South Florida, Tampa, FL. Aug’ 02 to Dec’04

Bachelor of Technology in Computer Science & Engineering GPA 3.7/4.0

J.N.T.U, Hyderabad, India. July’ 98 to May’ 02

Advanced Diploma In Satellite Engineering

CSRDC Hyderabad, India. July’ 98 to May’ 02

PROFESSIONAL EXPEREINCE

Computation of FFT’s for Chemical Molecular Structure (Aug 03 – present)

Role : Research Assistant, U.S.F Campus

Environment : Linux 9.0, C++, parallel programming,Shell Programming.

This Project is on computational chemistry of FFT’s (Fast Fourier Transform) where I seek data using parallel programming and computing using Linux .The aim of this project is the computation of Fast Fourier Transform using the FFTW software. This is

N.F.S (National Science Foundation) funded project.

Designing of Pressure Sensor ( Aug 02 - July 03)

Role : Research Assistant, U.S.F Campus

Environment : D.S.P Tool, Windows XP Professional, C++, Unix, Perl

Designing of the pressure sensor using G.P.S technology. The main aim is

to detect any holes in between concert piles in the concrete beams to make the pillars more strong . Worked on how the stress varies from point to point using the Matlab tool. The design layout of the sensor is developed through Cadence. This Project is N.S.F (National Science Foundation) funded.

INTERNSHIPS:

Functional Verification Intern Engineer Asic Labs, India (Jan-Jun 02)

Functional Verification of Board and FPGA Designs.

Verified networking boards with components like Altera FPGAs, SDRAM, FLASH, TDM Ports, and PCI interfaces, RISC Processors (IDT4650 & RM7000) and system Controllers. Verified FPGAs acting as IO controller or on the data-path. Developed the Test Plan, test scripts (using Verilog), simulation models (with timing details and checks in Verilog) and configured third party models like LMC (Logic Modeling Corporation) for PCI through PLIs. Generated Verilog board netlist from schematics and ran test vectors to check the connections at various interfaces, various jumper configurations on the board and also programmable logic on board. Generated various data patterns and verified the outputs using awaves. Simulated using Verilog XL and dynamic timing analysis using Virsim.

Graduate Intern Design Engineer, Nexxoft Infotel Ltd , India . (Jan-Jun 01)

Trained in System simulation, architecture verification for ASICs

Graduate Intern Design Engineer Tejas Networks Ltd ,India . (Jan-Jun 00)

Designed an 8 stage pipelined IP Forwarding Engine for fast address lookups. Implemented HDL Design, Simulation, Synthesis and Post synthesis Simulation using Verilog HDL, Cadence’s Verilog XL and Modelsim’s Design Analyzer tools

PROJECT EXPERIENCE

RF Projects :

LNA Design for CDMA Front End(Tools Lab View, Virtuso, Unix,Avan Waves)

Designed a front-end 900MHz and 1.9 GHz CDMA Low Noise Amplifier. The main emphasis was on Noise Figure, IP3, Gain and power dissipation trade offs. DC biasing represents the first step in LNA design. The chosen DC bias circuit should exhibit stable thermal performance and reduce the influence of hFE spread. It also should be a cost effective and simple solution, one that does not increase complexity of the design and preserves smallest possible size for the overall LNA.

PLL Synthesizer(Tools BrinaryProgramming,Shell Script,Perl, Hspice, Avan Waves)

This PLL-circuit uses a 9-bit BCD binary programmable divide-by-N counter, a Mixer and an X-Tal Oscillator to convert the output frequency f OUT to the f IN to the PLL Circuit. A PLL design may be categorized very generally by the number of crystals it uses, and by whether its VCO is running on the low or high side of 27 MHz. This particular PLL is actually the second generation of the PLL02A AM circuit; the original PLL circuit used a total of 3 crystals. The key to synthesizing all of the required frequencies lies in the Programmable Divider. That's the only PLL section that you can control from the outside world by means of the Channel Selector. Which is where it all starts.

VLSI Projects:

1024 Kb High-Speed SRAM Design (Tools Cadence, Hspice, Avan Waves)

Targeted and achieved designing high speed SRAM that runs at 333 MHz, occupies a total area of 38 um2 and has the worst case power dissipation of 10mw/write cycle. Logical Effort, Macro based design and Distributed Wordline scheme (DWL) was employed to boost speed. The circuitry designed included for READ/WRITE data path, SRAMcells, and fast decoders, Sense Amplifiers

High-Speed Parallel Link Transceiver (Tools Cadence, Hspice, Avan Waves)

Designed and implemented 2 GB/s/pin parallel link source-synchronous transceiver for high data throughput and minimal noise. Current signaling mode was employed at Transmitter and Sense Amplifier at the Receiver. The transmission line was taken as a 50 Ohm LC with a delay of 5 ns. Impedance matching was done at both ends for maximum power transfer. We achieved 8 Gbps (total of 4 data pins / 10 chip pins) using 0.25um CMOS technology. The circuitry designed included for Multiplexers, Current Signaling Mode Transmitters, and Sense Amplifiers.

Phase Locked Loop (PLL) (Tools Cadence, Hspice, Avan Waves)

Designed and simulated a PLL operating at 240 MHz for an IF Mixer. The Phase Frequency Detector was a flip-flop based design and the charge pump employed switched current sources. The Voltage Controlled Oscillator was a 3 stage Differential Mode Ring Oscillator with a free running frequency of around 240 MHz at 1.8v. The PLL acquired lock at around 8us. The circuitry designed were PFD, Charge Pump, VCO, frequency divider

Bandgap Reference Voltage (Tools Hspice, Avan Waves)

Designed a temperature independent Band gap reference of 1.25V using the PTAT concept. VBE of Bipolar transistors used as Negative Temperature Coefficient (NTC) and difference between VBE of 2 Bipolar transistors used as Positive Temperature Coefficient (PTC) was employed to generate the VRef . Op Amp was employed to provide feedback.

Content-Addressable Memory(Tools Hspice, Magic, Avan Waves)

Involved in the Design, extraction and simulation of 8x8 CAM array with 8-bit shift register and 4-bit row decoder and Study the speed, power consumption of this design.

Digital System Design and Testing

Design of 5-Stage Pipelined CPU (Tools ViewLogic, Powerview)

Designed and simulated Datapath and Control Logic for a single cycle, multi-cycle and 5-stage pipelined CPU (DLX Architecture) and 3-stage pipelined adder. The CPU supports 32-bit instructions of the load-store, arithmetic, branch and jump category.

ATPG Implementation for Combinational Circuits (Tools C)

Designed and implemented circuit models, simulation methods and test generations in C using Data structures. The circuit model is based on the ISCAS format on which PODEM and D-algorithm were implemented for generation of test vectors.

Semiconductor wafer fabrication

In 'Class 100' clean room, silicon wafers are processed and finished wafers were electrically tested for the extraction of the parameters of various devises on the wafer.

Design of a Traffic Signal Controller and 16-Bit ALU (Verilog)

Behavioral and structural description of the Traffic controller and ALU was designed, using Verilog gate / transistor primitives.

PC based wireless switching device (C)

A device was designed which Interfaces with PC and the Switching Circuit board. Microprocessor language and C language were used to implement this project.

Encoders And Decoder

Designing of Encoder And Decoder using V.H.D.L using Cadence NC launch.

16 Multiplexer

Designing of multiplexer using Verilog as sample for testing AUDI synthesis tool.

Implementation Of Data Path Synthesis Tool

This project uses knowledge of C, C++ and Java and finally the binding of

Various components is done using VHDL. This was project was checked using

AUDI system developed by one of the professor. This is a High Level Synthesis

Tool.

Designing of an interface circuit between a GPS receiver and Personal Computer

This projects includes the design of the chip using PIC controller and as well as

assembly language of 8051

DMA Construction

Construction of DMA controller using VHDL.

Vending Machine

Building of Vending Machine using Cadence tool.

Digital Signal Processing project

MATLAB use in digital signal processing to verify the motion of the human arm

TECHNICAL PAPERS WRITTEN

1 High Level Synthesis of Embedded Systems.

2 The advantage of DMA in comparison to CPU.

3 Optimization of power in circuits using Multiple Vdd, Multiple Threshold Voltages

4 Optimization of Power using Switching circuits

References and Availability

References available on request . Willing to Relocate.

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